
128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 47:
Alternating Bank Write Accesses
CLK
T0
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
T9
CKE
tCKS
tCMS
tCKH
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
DQM
tCMS
tCMH
tA S
tAH
A0–A9, A11
A10
ROW
tA S
tAH
ROW
COLUMN m 2
ENABLE AUTO PRECHARGE
ROW
ROW
COLUMN b 2
ENABLE AUTO PRECHARGE
ROW
ROW
tAS
tAH
BA0, BA1
BANK 0
BANK 0
BANK 1
BANK 1
BANK 0
t DS
tDH
t DS
tDH
t DS
tDH
t DS
tDH
t DS
tDH
t DS
tDH
tDS
tDH
t DS
tDH
DQ
D IN m
D IN m + 1
D IN m + 2
D IN m + 3
D IN b
D IN b + 1
D IN b + 2
D IN b + 3
tRCD - BANK 0
tWR - BANK 0
tRP - BANK 0
t RCD - BANK 0
tRAS - BANK 0
t RC - BANK 0
t RRD
Notes:
1. For this example, BL = 4.
2. A9 and A11 are “Don’t Care.”
tRCD - BANK 1
t WR - BANK 1
DON’T CARE
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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